The present invention relates to solid-state image sensors, and more particularly to a complementary metal-oxide-semiconductor (CMOS) image sensor having a pinned photodiode for light sensing and incorporating a charge transfer gate for transferring signal charge from the photodiode to a floating diffusion node. More specifically, the present invention relates to pixels using a correlated double sampling operation for minimizing kTC reset noise, incorporating blooming control therein, and having a very low dark current.
The typical image sensors sense light by converting impinging photons into electrons that are integrated in sensor pixels. After completing an integration cycle, collected charge is converted into a voltage, which is supplied to output terminals of the image sensor.
In typical CMOS image sensors, charge to voltage conversion is accomplished directly in pixels and an analog pixel voltage is transferred to output terminals through various pixel addressing and scanning schemes. The analog signal can also be converted to a digital equivalent on chip prior to reaching the chip output. A buffer amplifier, typically a source follower, is integrated in the pixel and drives the sense lines connected to the pixels by an addressing transistor.
After completing the charge to voltage conversion and transferring the signal out from the pixels, the pixels are reset in order to be ready for accumulation of new charge. With respect to pixels using a floating diffusion (FD) as a charge detection node, the reset is accomplished by turning on a reset transistor and momentarily conductively connecting the FD node to a reference voltage. Collected charge in the FD node is removed during the reset operation. However, kTC reset noise, as is well known in the art, is generated in the process of removing the collected charge in the FD node. kTC reset noise is removed by a correlated double sampling (CDS) signal processing technique in order to obtain a desired low noise performance.
The typical CMOS image sensors utilizing the CDS concept need to have four transistors (4T) in a pixel. One of the transistors is a charge transfer transistor transferring charge from a photodiode to a FD node. An example of the 4T pixel circuit is shown in the U.S. Pat. No. 5,625,210 issued to Lee.
Recently, a new pixel operating technique has been suggested, wherein only 3T are needed in the pixel. This is achieved by eliminating the addressing transistor from the pixel. Addressing of the pixel with 3T is accomplished by a source follower transistor itself by applying a predetermined bias on the FD nodes that are not selected. The recent description of this concept is shown in an article by Hidekazu Takahashi et al., entitled “A 1/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders,” ISSCC Digest of Technical Papers, pp. 510-511, 2007. Eliminating the addressing transistor from the pixel saves a valuable pixel area and also eliminates one control wire for controlling the gate of the addressing transistor.
Another technique for minimizing the number of transistors in a pixel is sharing pixel circuits with a plurality of photodiodes. An example of this design is shown in U.S. Pat. No. 6,657,665 B1 issued to Guidash. Guidash discloses a pixel consisting of two photodiodes located in neighboring rows that share the same circuits.
However, it is still necessary to transfer charge from a photodiode onto a FD node using a charge transfer transistor in all of those designs. The gate region of the charge transfer transistor should be designed such that the pixel performance is not degraded, this includes the charge transfer efficiency, blooming control, and dark current.
FIG. 1 illustrates a cross sectional view of a typical charge transfer transistor, a pinned photodiode and a floating diffusion.
A substrate 101 may be doped with p+-type impurities. A p-type impurity doped epitaxial layer 102 is formed over the p+-type impurity doped substrate 101. A pinned photodiode region including a p+-type impurity doped region 103 and an n-type impurity doped region 104, and a floating diffusion (FD) region 108 are formed in the p-type impurity doped epitaxial layer 102. A charge transfer gate 106 formed by polysilicon is formed over the epitaxial layer 102 and isolated from the p-type impurity doped epitaxial layer 102 by a gate insulation layer 111 that may include a silicon dioxide layer or some other insulation layer. The transfer gate 106 may also include sidewall spacers 105.
The metal interconnection 110 of the transfer gate 106 to a driving signal source is shown only schematically. The charge transfer transistor may also include a lightly doped drain (LDD) region 107. A p-type impurity doped region 109 is formed at an interface between the epitaxial layer 102 and the gate insulation layer 111 (Si—SiO2 interface) in order to minimize dark current.
Referring to FIG. 1, the p-type impurity doped region 109 is formed corresponding to a portion of a gate length, and thus most of the dark current generated at the Si—SiO2 interface flows into the FD region 108 rather than into the pinned photodiode.
The charge transfer gate is biased at 0 V during the normal operation of a pixel. When it is desirable to transfer charge from the pinned photodiode onto the FD region, the charge transfer gate may be pulsed with a positive pulse. The amplitude of the pulse may typically be the same as VDD bias of the sensor. However, the amplitude of the pulse may also be higher than the VDD bias when a positive charge pumping circuit is integrated on the sensor that can be used for biasing the gate drivers. The available positive amplitude of the transfer gate pulse limits the concentration of impurities that can be placed in the p-type impurity doped region 109 since a threshold voltage (VTX) of the transistor increases when the p-type impurities in the p-type impurity doped region 109 increases.
It is necessary that a difference between the VDD and the VTX is larger than a pinning voltage VPIN of the pinned photodiode in order to transfer all collected charge through the gate onto the FD region. Another reason for limiting the concentration of the impurities in the p-type impurity doped region 109 is charge transfer efficiency. The charge transfer efficiency may be reduced by higher concentration of the impurities in the p-type impurity doped region 109.
FIG. 2 illustrates a simplified potential energy band diagram of the typical charge transfer transistor shown in FIG. 1.
A conduction band 205 of an n+-type impurity doped polysilicon, i.e., the transfer gate, is lined up with a Quasi Fermi Level (QFL) 209 and with a valence band 202 of a p+-type impurity doped substrate at zero bias level. A gate insulation region 204 including silicon dioxide is biased by a certain built-in potential difference since the polysilicon is doped with n+-type impurities and the substrate is doped with p+-type impurities. The energy level of the conduction band of silicon substrate is indicated in a drawing in FIG. 2 as 201. A certain voltage difference equal to ΔV=EC−EV is approximately 1.0 V and is divided between the silicon, e.g. the substrate, and the silicon dioxide, e.g. the gate insulation region 204.
A portion of the voltage that is applied to the silicon causes band bending 208 and depopulation of interface states 206 of holes. Due to the depopulation, the interface states 206 generate electrons 207 that flow along the gate length in a direction perpendicular to the drawing into the pinned photodiode and the FD region. This electron flow contributes to dark current.
Portion of the voltage that is applied to the silicon dioxide and to the silicon depends on the thickness of the silicon dioxide and on the concentration of p-type impurities at the interface between the silicon and the silicon dioxide. It is desirable to apply most of the voltage to the silicon dioxide and minimize the band bending at the surface of the silicon. When the concentration of p-type impurities is increased, the band bending is decreased. However, when the concentration of p-type impurities is increased, the threshold voltage is increased and the charge transfer efficiency is decreased as described above. The concentration of the p-type impurities in the interface region 203 between the silicon dioxide and the silicon cannot exceed a maximum that is determined by the threshold voltage allowed in order to have a complete charge transfer.
In modern CMOS image sensors, the thickness of the gate insulation layer XOX 204 is very small and this results in a small voltage drop that can be developed across the gate insulation layer. This is a contradicting requirement for minimizing the band bending. The band bending at the interface between the silicon and the silicon dioxide is limited to a certain minimum value that cannot be further reduced due to both the maximum of the concentration of p-type impurities in the p-type impurity doped region 109 in the interface region 203 and the thin gate insulation layer XOX 204. Therefore, the typical transfer gate transistors have limitations that are difficult to overcome.
However, the band bending can also have a positive consequence, which is the blooming control. A potential well formed at the interface due to the band bending allows the overflow of charge from the photodiode to flow to the FD node, which then does not spread out into the neighboring pixels.